Quartus files

One of the biggest issues that I have, in general, while learning different stuff is lack of properly-explained abbreviations. I am starting today a compilation of Altera/ Intel Quartus list of filenames and abbreviations. Source: Intel/ Altera Glossary

• .qws – Quartus Workspace File. The Quartus^® Workspace File (.qws) is a non-editable file that stores user preferences and other information such as the position of the windows, the open files and their positions in the windows, and the windows information, such as docking status. This file is automatically generated.
• .acf – Assignment & Configuration File. This is an ASCII text file (with the extension .acf) that stores information about MAX+PLUS II assignments, as well as configuration settings for the Compiler, Simulator, and Timing Analyzer for an entire MAX+PLUS II project. The ACF stores information entered with menu commands in all MAX+PLUS II applications, as well as pin, location, and chip assignments entered in the MAX+PLUS II Floorplan Editor window.Note: You can import assignments from a MAX+PLUS II Assignment & Configuration File into the Quartus® Prime software with the Import Assignments command, but when you save the project, the Quartus® Prime software will save the file as a Quartus® Prime Settings File (.qsf).
• .atm – Atom Netlist File. A file (with the extension .atm, for example, .cmp.atm and .map.atm ) that is a version-compatible representation of internal database files
• .bdf – Block Design File. A schematic design file (with the extension .bdf) created with the Quartus® Prime Block Editor. Block Design Files may contain block diagrams, symbols, and schematics that represent logic in a design. You can read and edit Block Design Files in the Block Editor.
• .bsf – Block Symbol File. A symbol file created with the Quartus® Prime Symbol Editor. You can read and edit a symbol, which represents a macrofunction, primitive, megafunction, or design file, in a Block Symbol File, and add the symbol to a Block Design File (.bdf) with the Symbol Editor. You can also specify the ports and parameters of a symbol. The Symbol Editor allows you to open Library Mapping Files (.lmf); however, you must make the read-only Library Mapping Files writable before you edit them.
• .cmp – Component Declaration File. the IP Catalog generates a Component Declaration File which is a text file containing local generic and local port definitions that can be used in VHDL Design Files (.vhd).
• .csf – The Compiler Settings File is an ASCII file that stores the chip definitions for a Quartus^® project, the default device options, the compilation focus, the type of compilation to perform, the device family and device to use, and other options.
• .cof – Conversion Setup File. An ASCII text file  used to store information such as device and file names, device order, device properties, and file options. You can create and open Conversion Setup Files in the Convert Programming Files dialog box.
• .csv – Comma-Separated Value File. An ASCII text file, created from a table, in which each table cell in a row is represented by a value followed by a comma character. Each row ends with a newline character. You can create a Comma-Separated Value File for many sections in the Report window that contain tabular-format data by using the Save Current Report Section As command.
• .cvwf – Compressed Vector Waveform File. A compressed version, in binary format, of the Vector Waveform File, optimized to remove unnecessary information. This file describes simulation input vectors and simulation output vectors as graphical waveforms. More information here.
• license.dat – An ASCII text file containing the list of features, software expiration date, number of licenses, and other license information required to run the Quartus® Prime software on PC or Linux workstation.You can receive a license file by requesting one from the Licensing section of the Altera website at www.altera.com.
• .dpf – Design Protocol File. This file type is used by the Quartus® Prime software to store information. This file does not affect your assignments or settings. Pin assignments, I/O standard assignments, and all other assignment types are found in the Quartus® Prime Settings File for your project. It is not necessary to include files of this type in an archive of your project.
• .fcf – FLEX Chain File. An ASCII text file generated by the MAX+PLUS II software that stores programming file names when you configure multiple FPGA devices in Passive Serial mode. This file type is not generated by the Quartus® Prime software and is supported only for backward compatibility.
• .gdf – Graphic Design File. A schematic design file (with the extension .gdf) created with the MAX+PLUS II Graphic Editor. You can read and edit Graphic Design Files with the Quartus® Prime Block and Symbol Editors; however, the Quartus® Prime software saves the Graphic Design Files as Block Design Files (.bdf). If the Graphic Design Files contain symbols created in the MAX+PLUS DOS software, the Quartus® Prime software can read the symbols if you update the symbols with the Update Symbol or Block command.
• .hex – Hexadecimal (Intel-Format) File. An ASCII text file (with the extension .hex). You can use a Hexadecimal (Intel-Format) File (.hex) in the Quartus® Prime software to store the initial memory values for a memory block, such as RAM or ROM, that is implemented in an FPGA device, or to build software project executables. You can use .hex files as input files in the Quartus® Prime software in the following ways:
  • The Memory Editor can create a .hex file for memory initialization in the Compiler and Simulator. You can also use a Memory Initialization File (.mif) to provide memory initialization data.
  • The In-System Memory Content Editor can use and create a .hex file to import and export data.
• .hexout – Hexadecimal (Intel-Format) Output File. An ASCII text file, that is in the Intel hexadecimal format and contains configuration data for use outside the Quartus® Prime software. See here
• .sp – HSPICE Simulation Deck File. An ASCII text file (with the extension .sp) that contains an HSPICE Simulation Deck for a specific pin, generated by the Quartus® Prime software for performing board-level signal integrity analysis of Intel devices with other EDA tools.
• ._hw.tcl – Component Description File. A Tcl file with the file name of the form <entity name>_hw.tcl. The ._hw.tcl file is the underlying format of many Intel-provided IP cores available in the Quartus® Prime software, including Qsys Pro components and MegaCore® functions. When you create custom IP components in the Qsys Pro Component Editor, the component is saved in the ._hw.tcl format. After your component is created in a ._hw.tcl file, you can add instances of your component to a Qsys Pro system, which can then be generated to create output HDL files (Verilog or VHDL) for your Quartus® Prime project.
• .inc – AHDL Include File. An ASCII text file (with the extension .inc) that can be imported into a Text Design File (.tdf) by an AHDL Include Statement. The AHDL Include File replaces the Include Statement that calls it. AHDL Include Files can contain Function Prototype, Define, Parameters, or Constant Statements. AHDL Include Files that contain Function Prototypes for Intel-provided megafunctions are located in the \quartus\libraries\megafunctions and \quartus\libraries\others\maxplus2 directories created during installation.
• .ips – I/O Pin State File Definition. An ASCII text file containing pin state information for specific devices used to configure pin states during programming. You can create IPS Files by pointing to Create/Update and then clicking IPS File on the File menu. You can also assign pin states to pins using logic options in the Assignment Editor. Pin state assignments made in the Assignment Editor are stored in the Quartus® Prime Settings File (.qsf) or Programmer Object File (.pof) and are overridden during programming by any changes defined in an IPS File.
• .ipx – IP Index File. An XML file whose top-level element is <library>. The two legal subelements are <path> and <component>. Each IP Index File indexes a collection of available SOP Builder components. The IP Index Files then facilitate faster startup for SOPC Builder and other tools because fewer files need to be read and analyzed. The SOPC Builder component search path searches some directories recursively, while others are only searched to a specific depth. In the following list of search locations, a recursive descent is annotated by **. The * signifies any file. When a directory is recursively searched, the search stops at any directory containing either a Component Description File (hw.tcl)or an IP Index File; subdirectories are not searched.
  • $$PROJECT_DIR/*
  • $$PROJECT_DIR/ip/**/*