Tag Archives: Intel

Altera Qsys, NIOS II and FPGA fun

One very interesting feature of Altera FPGAs is that almost any system can be created in its next-generation system integration tool Qsys using a standard library of reusable IP blocks. The system interconnect fabric is automatically generated by Qsys and binds the blocks together. The system interconnect manages dynamic bus with matching, interrupt priorities, arbitration …

Posted on martie 20, 2018 by AP