Altera Qsys, NIOS II and FPGA fun

Building a complete softcore processor


One very interesting feature of Altera FPGAs is that almost any system can be created in its next-generation system integration tool Qsys using a standard library of reusable IP blocks. The system interconnect fabric is automatically generated by Qsys and binds the blocks together. The system interconnect manages dynamic bus with matching, interrupt priorities, arbitration and address mapping. When NIOS II softcore processor is included,  this system is a full feature processor system capable of running operating systems such as Micro SIOS II, or Linux. During the course I was guided through the process of building a basic embedded system. I built up a subset of a system block diagram provided as part of the lectures, one block at a time, one step at a time.

Qsys — adding a PLL core using the Qsys ALTPLL megawizard

Altera Qsys: clock connections in editor window

As all control algorithms need a CPU to run and the „wow” factor of this is the possibility to add a complete softcore processor, a NIOS II processor. The NIOS II is a 32 bit CPU built in FPGA programmable logic, with a number of distinct benefits. It can easily be configured and can be customized to include just the desired functions. Many functions of the core are optional, but combined with the available bus interconnects in Qsys, it is very easy to extend the processor system to include a wide range of memory and peripherals. Since it allows to include on a per-need basis, the resource usage can be very efficient. The performance is optimized, the speed is quite ok (not what one would expect from a hardcore processor though). However — and this is the biggest plus — unlike hardcore processors obsolescence is not a problem: once designed, the softcore system can be applied to FPGA now and into the future.

Altera Qsys: NIOS II processor configuration options

To summarize, Qsys is a powerful and easy to use tool to create complete systems using block diagram concepts with detailed connections. Rather than designing a CPU in logic from scratch, a better alternative is to use existing CPU designs like Altera’s NIOS II. The design can be done very quickly, and is optimized for performance and resource usage.

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End of week — pin planner

This week was quite busy to complete my assignments for the FPGA Course. I was running out of time because I did not estimate properly my available free time and things got crowded at the office, at this end of week. With a lot to do there, I barely found any time to focus on […]

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