End of week — pin planner

This is more like a diary entry


This week was quite busy to complete my assignments for the FPGA Course. I was running out of time because I did not estimate properly my available free time and things got crowded at the office, at this end of week. With a lot to do there, I barely found any time to focus on my personal projects. Probably my age starts to tell me something like: „take it slowly, you need more rest, less hassle…” but what the heck !

Today I learned how to do pin assignments in Altera‘s Quartus Prime. Quartus Prime is an amazing tool and provides a dedicated Pin Planner tool to assist the pin assignment process. This is a very important step for any FPGA. Once the schematic is completed and optimization is done (or time closure is achieved), the last step before proceeding to programming (and, probably, to optimization of PCB design) is the pin assignment, which means that you have to assign schematic entries to some physical device pins. Although it seems that pin assignment might also follow the PCB design process — I still have to understand correctly the best practices in this — PCB design is out of the scope of this course.

Today I learned how to assign pins to my design using the Pin Planner and the Assignment Editor and how to check my pin assignments using the IO assignment analyzer. Overall, I am impressed by this course. I hope that peers will keep their promise and release the rest of the courses in this specialization.

Altera Qsys, NIOS II and FPGA fun

One very interesting feature of Altera FPGAs is that almost any system can be created in its next-generation system integration tool Qsys using a standard library of reusable IP blocks. The system interconnect fabric is automatically generated by Qsys and binds the blocks together. The system interconnect manages dynamic bus with matching, interrupt priorities, arbitration […]

FPGA Course

I’ve been quite busy lately and neglected the blog. I enrolled on Coursera for a very interesting FPGA course, in what seems to be a FPGA specialization from University of Colorado Boulder. I have always had somewhat a reserved attitude towards FPGAs mainly because I believed that these are hard to understand and need a […]

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